LAN9303 Datasheet, PDF (104/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

7.3.1.3
7.3.2
7.3.2.1
7.3.3
7.3.3.1
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
Virtual PHY Pause Flow Control
The Virtual PHY supports pause flow control per the IEEE 802.3 specification. The Virtual PHYs
advertised pause flow control abilities are set via the Symmetric Pause and Asymmetric Pause bits of
the Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV). This allows the Virtual
PHY to advertise its flow control abilities and auto-negotiate the flow control settings with the emulated
link partner. The default values of these bits are as shown in Section 13.2.6.5, "Virtual PHY Auto-
Negotiation Advertisement Register (VPHY_AN_ADV)," on page 176.
The symmetric/asymmetric pause ability of the emulated link partner is based upon the advertised
pause flow control abilities of the Virtual PHY as indicated in the Symmetric Pause and Asymmetric
Pause bits of the Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV). Thus, the
emulated link partner always accommodates the asymmetric/symmetric pause ability settings
requested by the Virtual PHY, as shown in Table 13.6, “Emulated Link Partner Pause Flow Control
Ability Default Values,” on page 179.
The pause flow control settings may also be manually set via the Port 0 Manual Flow Control Register
(MANUAL_FC_0). This register allows the Switch Fabric Port 0 flow control settings to be manually
set when auto-negotiation is disabled or the Port 0 Full-Duplex Manual Flow Control Select
(MANUAL_FC_0) bit is set. The currently enabled duplex and flow control settings can also be
monitored via this register. The flow control values in the Virtual PHY Auto-Negotiation Advertisement
Register (VPHY_AN_ADV) are not affected by the values of the manual flow control register. Refer to
Section 6.2.3, "Flow Control Enable Logic," on page 62 for additional information.
Virtual PHY in MAC Mode
In the MAC mode of operation, an external PHY is connected to the MII interface of the device.
Because there is an external PHY present, the Virtual PHY is not needed for external configuration.
However, the Port 0 Switch Fabric MAC still requires the proper duplex setting. Therefore, in MAC
mode, if the Auto-Negotiation (VPHY_AN) bit of the Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL) is set, the duplex is based on the P0_DUPLEX pin and duplex_pol_strap_0
configuration strap. If these signals are equal, the Port 0 Switch Fabric MAC is configured for full-
duplex, otherwise it is set for half-duplex. The P0_DUPLEX pin is typically connected to the duplex
indication of the external PHY. The duplex is not latched since the auto-negotiation process is not used.
The duplex can be manually selected by clearing the Auto-Negotiation (VPHY_AN) bit and controlling
the Duplex Mode (VPHY_DUPLEX) bit in the Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL).
Note: In MAC mode, the Virtual PHY registers are accessible through their memory mapped registers
via the SMI or I²C serial management interfaces only. The Virtual PHY registers are not
accessible through MII management.
Full-Duplex Flow Control
In the MAC mode of operation, the Virtual PHY is not applicable. Therefore, full-duplex flow control
should be controlled manually by the host via the Port 0 Manual Flow Control Register
(MANUAL_FC_0), based on the external PHYs auto-negotiation results.
Virtual PHY Resets
In addition to the chip-level hardware reset (nRST) and Power-On Reset (POR), the Virtual PHY
supports two block specific resets. These are is discussed in the following sections. For detailed
information on all resets, refer to Section 4.2, "Resets," on page 42.
Virtual PHY Software Reset via RESET_CTL
The Virtual PHY can be reset via the Reset Control Register (RESET_CTL) by setting the Virtual PHY
Reset (VPHY_RST) bit. This bit is self clearing after approximately 102uS.
Revision 1.3 (08-27-09)
104
DATASHEET
SMSC LAN9303/LAN9303i