LAN9303 Datasheet, PDF (271/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
13.4.3 Switch Engine CSRs
This section details the Switch Engine related CSRs. These registers allow configuration and
monitoring of the various Switch Engine components including the ALR, VLAN, Port VID, and
DIFFSERV tables. A list of the general switch CSRs and their corresponding register numbers is
included in Table 13.14.
13.4.3.1 Switch Engine ALR Command Register (SWE_ALR_CMD)
Register #:
1800h
Size:
32 bits
This register is used to manually read and write MAC addresses from/into the ALR table.
For a read access, the Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0) and Switch
Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1) should be read following the setting of the
Get First Entry bit or Get Next Entry bit of this register.
For write access, the Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0) and Switch
Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) registers should first be written with the
MAC address, followed by the setting of the Make Entry bit of this register. The Make Pending bit in
the Switch Engine ALR Command Status Register (SWE_ALR_CMD_STS) register indicates when the
command is finished.
Refer to Chapter 6, "Switch Fabric," on page 59 for more information.
BITS
DESCRIPTION
31:3 RESERVED
2 Make Entry
When set, the contents of SWE_ALR_WR_DAT_0 and
SWE_ALR_WR_DAT_1 are written into the ALR table. The ALR logic
determines the location where the entry is written. This command can also
be used to change or delete a previously written or automatically learned
entry. This bit has no affect when written low. This bit must be cleared once
the ALR Make command is completed, which can be determined by the
Make Pending bit in the Switch Engine ALR Command Status Register
(SWE_ALR_CMD_STS) register.
1 Get First Entry
When set, the ALR read pointer is reset to the beginning of the ALR table
and the ALR table is searched for the first valid entry, which is loaded into
the SWE_ALR_RD_DAT_0 and SWE_ALR_RD_DAT_1 registers. The bit
has no affect when written low. This bit must be cleared after it is set.
0 Get Next Entry
When set, the next valid entry in the ALR MAC address table is loaded into
the SWE_ALR_RD_DAT_0 and SWE_ALR_RD_DAT_1 registers. This bit
has no affect when written low. This bit must be cleared after it is set.
TYPE
RO
R/W
R/W
R/W
DEFAULT
-
0b
0b
0b
SMSC LAN9303/LAN9303i
271
DATASHEET
Revision 1.3 (08-27-09)