LAN9303 Datasheet, PDF (126/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

10.2.2
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
Write Sequence
In a write sequence, the host sends the 32-bit preamble, 2-bit start of frame, 2-bit op-code, 5-bit PHY
Address, 5-bit Register Address, 2-bit turn-around time, and finally the 16-bits of data. The MDIO pin
is three-stated throughout the write sequence.
The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD
transfer. No ordering requirement exists. The host may access either the low or high word first, as long
as the next write is performed to the opposite word. If a write to the same word is performed, the device
disregards the transfer.
Note: SMI writes must not be performed to unused register addresses.
10.3 PHY Management Interface (PMI)
The PHY Management Interface (PMI) is used to access the internal PHYs as well as the external
PHY on the MII pins (in MAC modes only). The PMI operates at 2.5MHz, and implements the IEEE
802.3 management protocol, providing read/write commands for PHY configuration.
A read or write is performed using the frame format shown in Table 10.2. All addresses and data are
transferred msb first. Data bytes are transferred little endian.
Table 10.2 MII Management Frame Format
PREAMBLE
START
OP
CODE
PHY
ADDRESS
REGISTER
ADDRESS
TURN-
AROUND
TIME
Note 10.4
DATA
IDLE
Note
10.5
READ
WRITE
32 1’s
32 1’s
01
10
AAAAA
RRRRR
01
01
AAAAA
RRRRR
Z0
DDDDDDDDDDDDDDDD
Z
10
DDDDDDDDDDDDDDDD
Z
10.3.1
Note 10.4
The turn-around time (TA) is used to avoid bus contention during a read cycle. For a read,
the external PHY drives the second bit of the turn-around time to 0, and then drives the
msb of the read data in the following cycle. For a write, the device drives the first bit of
the turnaround time to 1, the second bit of the turnaround time to 0, and then the msb of
the write data in the following clock cycle.
Note 10.5 In the IDLE condition, the MDIO output is three-stated and pulled high externally.
The internal PHYs and optional external PHY (in MAC modes) are accessed via the PHY Management
Interface Access Register (PMI_ACCESS) and PHY Management Interface Data Register
(PMI_DATA). These registers allow read and write operations to all PHY registers. Refer to Section
13.2.5, "PHY Management Interface (PMI)," on page 167 for detailed information on these registers.
EEPROM Loader PHY Register Access
The PMI is also used by the EEPROM Loader to load the PHY registers with various configuration
strap values. The PHY Management Interface Access Register (PMI_ACCESS) and PHY Management
Interface Data Register (PMI_DATA) are also accessible as part of the Register Data burst sequence
of the EEPROM Loader. Refer to Section 8.4, "EEPROM Loader," on page 113 for additional
information.
Revision 1.3 (08-27-09)
126
DATASHEET
SMSC LAN9303/LAN9303i