LAN9303 Datasheet, PDF (111/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
exception that a slave device can only extend the low time of the clock. It can not cause the falling
edge of the clock.
8.3.6.3
Arbitration
Arbitration involves testing the input data vs. the output data, when the clock goes high, to see if they
match. Since the data line is wired-AND’ed, a master transmitting a high value will see a mismatch if
another master is transmitting a low value. The comparison is not done when receiving bits from the
slave. Arbitration starts with the control byte and, if both masters are accessing the same slave, can
continue into address and data bits (for writes) or acknowledge bits (for reads). If desired, a master
that loses arbitration can continue to generate clock pulses until the end of the loosing byte (note that
the ACK on a read is considered the end of the byte) but the losing master may no longer drive any
data bits. It is not permitted for another master to access the EEPROM while the device is using it
during startup or due to an EEPROM command. The other master should wait sufficient time or poll
the device to determine when the EEPROM is available. This restriction simplifies the arbitration and
access process since arbitration will always be resolved when transmitting the 8 control bits during the
Device Addressing or during the Poll Cycles. If arbitration is lost during the Device Addressing, the I²C
Master will return to the beginning of the Device Addressing sequence and wait for the bus to become
free. If arbitration is lost during a Poll Cycle, the I²C Master will return to the beginning of the Poll
Cycle sequence and wait for the bus to become free. Note that in this case the 30mS time out counter
should not be reset. If the 30mS timeout should expire while waiting for the bus to become free, the
sequence should not abort without first completing a final poll (with the exception of the busy /
arbitration timeout described in Section 8.3.6.4).
8.3.6.4
8.3.7
Timeout Due to Busy or Arbitration
It is possible for another master to monopolize the bus (due to a continual bus busy or more successful
arbitration). If successful arbitration is not achieved within 1.92 seconds from the start of the read or
write request or from the start of the Poll cycle, the command sequence or Poll cycle is aborted and
the EEPROM Controller Timeout (EPC_TIMEOUT) bit in the EEPROM Command Register
(E2P_CMD) is set. Note that this is a total timeout value and not the timeout for any one portion of
the sequence.
I²C Master EEPROM Controller Operation
I²C master EEPROM operations are performed using the EEPROM Command Register (E2P_CMD)
and EEPROM Data Register (E2P_DATA).
The following operations are supported:
„ READ (Read Location)
„ WRITE (Write Location)
„ RELOAD (EEPROM Loader Reload - See Section 8.4, "EEPROM Loader")
Note: The EEPROM Loader uses the READ command only.
The supported commands are detailed in Section 13.2.3.1, "EEPROM Command Register
(E2P_CMD)," on page 148. Details specific to each operational mode are explained in Section 8.2,
"I2C Overview" and Section 8.4, "EEPROM Loader", respectively.
When issuing a WRITE command, the desired data must first be written into the EEPROM Data
Register (E2P_DATA). The WRITE command may then be issued by setting the EEPROM Controller
Command (EPC_COMMAND) field of the EEPROM Command Register (E2P_CMD) to the desired
command value. If the operation is a WRITE, the EEPROM Controller Address (EPC_ADDRESS) field
in the EEPROM Command Register (E2P_CMD) must also be set to the desired location. The
command is executed when the EEPROM Controller Busy (EPC_BUSY) bit of the EEPROM
Command Register (E2P_CMD) is set. The completion of the operation is indicated when the
EEPROM Controller Busy (EPC_BUSY) bit is cleared.
When issuing a READ command, the EEPROM Controller Command (EPC_COMMAND) and
EEPROM Controller Address (EPC_ADDRESS) fields of the EEPROM Command Register
SMSC LAN9303/LAN9303i
111
DATASHEET
Revision 1.3 (08-27-09)