K524G2GACB-A050 Datasheet, PDF (73/94 Pages) Samsung semiconductor – MCP MEMORY

K524G2GACB-A050
MCP MEMORY
14. Burst Stop
The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock(CK). The burst stop
command has the fewest restrictions making it the easiest method to use when terminating a burst read operation before it has been com-
pleted. When the burst stop command is issued during a burst read cycle, the pair of data and DQS(Data Strobe) go to a high impedance state
after a delay which is equal to the CAS latency set in the mode register. However, the burst stop command is not supported during a burst
write operation.
Figure 10. Burst stop timing
0
1
2
3
4
5
6
7
8
CK
CK
Command READ A Burst Stop
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS
Hi-Z
DQs
Hi-Z
The burst read ends after a delay equal to the CAS latency.
Dout 0 Dout 1
NOTE :
1) Burst Length=4, CAS Latency= 3
The Burst Stop command is a mandatory feature for Mobile DDR SDRAM. The following functionality is required:
1. The Burst Stop command may only be issued on the rising edge of the input clock, CK.
2. Burst Stop is only a valid command during Read bursts.
3. Burst Stop during a Write burst is undefined and shall not be used.
4. Burst Stop applies to all burst lengths.
5. Burst Stop is an undefined command during Read with autoprecharge and shall not be used.
6. When terminating a burst Read command, the BST command must be issued L_BST (“BST Latency”) clock cycles before the clock
edge at which the output buffers are tristated, where L_BST equals the CAS latency for read operations.
7. When the burst terminates, the DQ and DQS pins are tristated.
The Burst Stop command is not byte controllable and applies to all bits in the DQ data word and the(all) DQS pin(s).
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Revision 1.3
November 2009