K524G2GACB-A050 Datasheet, PDF (15/94 Pages) Samsung semiconductor – MCP MEMORY

K524G2GACB-A050
MCP MEMORY
1.4 VALID BLOCK
Parameter
4Gb
8Gb DDP
Symbol
NVB
NVB
Min
4,016
8.032
Typ.
-
-
Max
4,096
8,192
Unit
Blocks
Blocks
NOTE :
1) The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented
with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad
blocks. Refer to the attached technical notes for appropriate management of invalid blocks.
2) The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with x8 : 1bit/ 512Byte, x16 : 1bit/
256Word ECC.
3) Each mono chip in th KF88GxxQ2W has maximum 40 invalid blocks.
1.5 AC TEST CONDITION
(TA=-25 to 85°C, Vcc=1.7V~1.95V unless otherwise noted)
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
Value
0V to Vcc
5ns
Vcc/2
1 TTL GATE and CL=30pF
1.6 CAPACITANCE(TA=25°C, VCC=1.8V, f=1.0MHz)
Item
Symbol
Test Condition
Min
Input/Output Capacitance (Mono)
CI/O
VIL=0V
-
Input Capacitance (Mono)
CIN
VIN=0V
-
Input/Output Capacitance (DDP)
CI/O
VIL=0V
-
Input Capacitance (DDP)
CIN
VIN=0V
-
NOTE :
Capacitance is periodically sampled and not 100% tested.
Max
10
10
20
20
Unit
pF
pF
pF
pF
1.7 MODE SELECTION
CLE
ALE
CE
WE
H
L
L
L
H
L
H
L
L
L
H
L
L
L
L
L
L
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X⁽¹⁾
X
X
X
X
H
X
NOTE :
1) X can be VIL or VIH.
2) WP should be biased to CMOS high or CMOS low for standby.
RE
WP
Mode
H
X
Command Input
Read Mode
H
X
Address Input(5clock)
H
H
Command Input
Write Mode
H
H
Address Input(5clock)
H
H
Data Input
X
Data Output
H
X
During Read(Busy)
X
H
During Program(Busy)
X
H
During Erase(Busy)
X
L
Write Protect
X
0V/VCC⁽²⁾ Stand-by
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Revision 1.3
November 2009