K524G2GACB-A050 Datasheet, PDF (65/94 Pages) Samsung semiconductor – MCP MEMORY

K524G2GACB-A050
MCP MEMORY
3. Row Active
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock(CK). The Mobile
DDR SDRAM has four independent banks, so two Bank Select addresses(BA0, BA1) are required. The Bank Activation command must be
applied before any Read or Write operation is executed. The delay from the Bank Activation command to the first read or write command must
meet or exceed the minimum of RAS to CAS delay time, tRCD(min). Once a bank has been activated, it must be precharged before another
Bank Activation command can be applied to the same bank. The minimum time interval between interleaved Bank Activation commands(Bank
A to Bank B and vice versa) is the Bank to Bank delay time, tRRD(min).
Any system or application incorporating random access memory products should be properly designed, tested and qulifided to ensure proper
use or access of such memory products. Disproportionate, excessive and/or repeated access to a particular address or addresses may result
in reduction of product life.
Figure 1. Bank Activation Command Cycle timing <tRCD=3CLK , tRRD=2CLK>
0
1
2
CK
CK
3
4
5
Tn
Tn+1
Tn+2
Bank A
Address _{Row Addr.}
Command
Bank A
Activate
Bank A
Col. Addr.
RAS-CAS delay(tRCD)
NOP
NOP
Write A
with Auto
Precharge
NOP
NOP
Bank B
Row Addr.
Bank A
Row. Addr.
RAS-RAS delay time(tRRD)
Bank B
Activate
NOP
Bank A
Activate
ROW Cycle Time(tRC)
: Don′t care
4. Read Bank
This command is used after the row activate command to initiate the burst read of data. The read command is initiated by activating RAS, CS,
CAS, and WE at the same clock sampling(rising) edge as described in the command truth table. The length of the burst and the CAS latency
time will be determined by the values programmed during the MRS cycle.
5. Write Bank
This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating RAS, CS,
CAS, and WE at the same clock sampling(rising) edge as described in the command truth table. The length of the burst will be determined by
the values programmed during the MRS cycle.
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Revision 1.3
November 2009