K524G2GACB-A050 Datasheet, PDF (40/94 Pages) Samsung semiconductor – MCP MEMORY

K524G2GACB-A050
MCP MEMORY
4.6 Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five
read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th, 5th cycle ID respectively. The command reg-
ister remains in Read ID mode until further commands are issued to it. Figure 14 shows the operation sequence.
CLE
CE
WE
ALE
RE
I/OX
Figure 14. Read ID Operation
tCLR
tCEA
tAR
tWHR
90h
00h
Address. 1cycle
tREA
ECh
Maker code
Device
Code
3rd Cyc.
Device code
4th Cyc. 5th Cyc.
Device
4Gb(x8)
8Gb DDP(x8)
4Gb(x16)
8Gb DDP(x16)
Device Code (2nd Cycle)
ACh
A3h
BCh
B3h
3rd Cycle
00h
01h
00h
01h
4th Cycle
15h
15h
55h
55h
5th Cycle
54h
58h
54h
58h
4.7 RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, pro-
gram or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the
data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared
to value C0h when WP is high. If the device is already in reset state a new reset command will be accepted by the command register. The R/
B pin changes to low for tRST after the Reset command is written. Refer to Figure 15 below.
R/B
I/OX
FFh
Operation mode Mode
Figure 15. RESET Operation
tRST
Table 5. Device Status
After Power-up
00h Command is latched
After Reset
Waiting for next command
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Revision 1.3
November 2009