K524G2GACB-A050 Datasheet, PDF (4/94 Pages) Samsung semiconductor – MCP MEMORY

K524G2GACB-A050
MCP MEMORY
3. GENERAL DESCRIPTION
The K524G2GACB is a Multi Chip Package Memory which combines 4Gbit NAND Flash Memory an 2Gbit DDR synchronous high data rate
Dynamic RAM.
NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical
250µs on the (1K+32)Word page and an erase operation can be performed in typical 2ms on a (64K+2K)Word block. Data in the data register
can be read out at 42ns cycle time per Word. The I/O pins serve as the ports for address and data input/output as well as command input. The
on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and
margining of data. Even the write-intensive systems can take advantage of the device′s extended reliability of 100K program/erase cycles by
providing ECC(Error Correcting Code) with real time mapping-out algorithm. The device is an optimum solution for large nonvolatile storage
applications such as solid state file storage and other portable applications requiring non-volatility.
In 2Gbit Mobile DDR, Synchronous design make a device controlled precisely with the use of system clock. Range of operating frequencies,
programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance
memory system applications.
The K524G2GACB is suitable for use in data memory of mobile communication system to reduce not only mount area but also power con-
sumption. This device is available in 137-ball FBGA Type.
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Revision 1.3
November 2009