K524G2GACB-A050 Datasheet, PDF (12/94 Pages) Samsung semiconductor – MCP MEMORY

K524G2GACB-A050
MCP MEMORY
Figure 3. Functional Block Diagram(x16)
VCC
VSS
A11 - A29*
X-Buffers
Latches
& Decoders
4,096M + 128M Bit for 4Gb
8,192M + 256M Bit for 8Gb DDP
NAND Flash
ARRAY
A0 - A10
Y-Buffers
Latches
& Decoders
Data Register & S/A
Y-Gating
Command
Command
Register
CE
Control Logic
RE
& High Voltage
WE
Generator
CLE ALE WP
I/O Buffers & Latches
VCC
VSS
Global Buffers
Output
Driver
I/0 0
I/0 15
Figure 4. Figure 2-2. Array Organization(x16)
1 Block = 64 Pages
(64K + 2K)Word
4,096 blocks for 4Gb
8,192 blocks for 8Gb DDP
1K Words
32 Words
1 Page = (1K + 32)Word
1 Block = (1K + 32)Word x 64 Pages
= (64K + 2K)Words
1 Device = (1K + 32)Word x 64Pages x 4,096 Blocks
= 4,224 Mbits for 4Gb
16 bit ^{1 Device = (1K + 32)Word x 64Pages x 8,192 Blocks}
= 8,448 Mbits for 8Gb DDP
I/O 0 I/O 1
Page Register
1K Words
I/O 0 ~ I/O 15
32 Words
Table 2. Array address : (x16)
I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8~I/O 15
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
*L
2nd Cycle
A8
A9
A10
*L
*L
*L
*L
*L
*L
3rd Cycle
A11
A12
A13
A14
A15
A16
A17
A18
*L
4th Cycle
A19
A20
A21
A22
A23
A24
A25
A26
*L
5th Cycle
A27
A28
*A29
*L
*L
*L
*L
*L
*L
NOTE :
Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than required.
* A29 is Row address for 8G DDP.
In case of 4G Mono, A29 must be set to "Low"
Address
Column Address
Column Address
Row Address
Row Address
Row Address
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Revision 1.3
November 2009