K524G2GACB-A050 Datasheet, PDF (53/94 Pages) Samsung semiconductor – MCP MEMORY

K524G2GACB-A050
7. AC Timming Parameters & Specifications
Parameter
Symbol
Clock cycle time
Row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Active delay
Last data in to Read command
CL=3
tCK
tRC
tRAS
tRCD
tRP
tRRD
tWR
tDAL
tCDLR
Col. address to Col. address delay
tCCD
Clock high level width
Clock low level width
DQ Output data access time from CK/CK CL=3
DQS Output data access time from CK/CK CL=3
Data strobe edge to ouput data edge
Read Preamble
CL=3
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS-in high level width
DQS-in low level width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
DQS-in cycle time
Address and Control
Input setup time
fast slew
rate
slow slew
rate
Address and Control
Input hold time
fast slew
rate
slow slew
rate
Address & Control input pulse width
DQ & DM setup time to DQS
fast slew
rate
slow slew
rate
DQ & DM hold time to DQS
fast slew
rate
slow slew
rate
DQ & DM input pulse width
DQ & DQS low-impedence time from CK/CK
DQ & DQS high-impedence time from CK/CK
DQS write postamble time
tCH
tCL
tAC
tDQSCK
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tDQSH
tDQSL
tDSS
tDSH
tDSC
tIS
tIH
tIPW
tDS
tDH
tDIPW
tLZ
tHZ
tWPST
DDR400
Min
Max
5
55
40
70,000
20
15
10
12
-
2
1
0.45
0.55
0.45
0.55
2
5
2
5
0.4
0.9
1.1
0.4
0.6
0.75
1.25
0
0.25
0.4
0.6
0.4
0.6
0.2
0.2
0.9
1.1
0.9
1.1
0.9
1.1
2.2
0.48
0.58
0.48
0.58
1.2
1.0
5
0.4
0.6
MCP MEMORY
DDR333
Min
Max
6
60
42
70,000
18
18
12
12
-
1
1
0.45
0.55
0.45
0.55
2
5.5
2
5.5
0.5
0.9
1.1
0.4
0.6
0.75
1.25
0
0.25
0.4
0.6
0.4
0.6
0.2
0.2
0.9
1.1
1.1
1.3
1.1
1.3
2.2
0.6
0.7
0.6
0.7
1.2
1.0
5.5
0.4
0.6
Unit Note
ns
1,2
ns
ns
ns
ns
ns
ns
-
3
tCK
tCK
tCK
tCK
ns
4
ns
ns
tCK
tCK
tCK
ns
5
tCK
tCK
tCK
tCK
tCK
tCK
7
ns
8
ns
7
8
6,7
ns
6,8
6,7
ns
6,8
ns
ns
ns
tCK
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Revision 1.3
November 2009