K524G2GACB-A050 Datasheet, PDF (54/94 Pages) Samsung semiconductor – MCP MEMORY

K524G2GACB-A050
MCP MEMORY
Parameter
DQS write preamble time
Refresh interval time
Mode register set cycle time
Power down exit time
CKE min. pulse width(high and low pulse width)
Auto refresh cycle time
Exit self refresh to active command
Data hold from DQS to earliest DQ edge
Data hold skew factor
Clock half period
Symbol
tWPRE
tREF
tMRD
tPDEX
tCKE
tRFC
tXSR
tQH
tQHS
tHP
DDR400
Min
Max
0.25
64
2
2
2
120
120
tHPmin -
tQHS
0.5
tCLmin or
tCHmin
DDR333
Min
Max
0.25
64
2
1
2
120
120
tHPmin -
tQHS
0.65
tCLmin or
tCHmin
Unit Note
tCK
ms
tCK
tCK
tCK
ns
9
ns
ns
ns
ns
NOTE :
1) tCK(max) value is measured at 100ns.
2) The only time that the clock Frequency is allowed to be changed is during clock stop, power-down, self-refresh modes.
3) In case of below 33MHz (tCK=30ns) condition, SEC could support tDAL(=2*tCK).
tDAL =(tWR/tCK) + (tRP/tCK)
4) tAC(min) value is measured at the high Vdd(1.95V) and cold temperature(-25°C).
tAC(max) value is measured at the low Vdd(1.7V) and hot temperature(85°C).
tAC is measured in the device with half driver strength and under the AC output load condition (Fig.6 in next Page).
5) The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no
writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS.
6) I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Data Rise/Fall Rate
(ns/V)
0
±0.25
±0.5
∆tDS
(ps)
0
+50
+100
∆tDH
(ps)
0
+50
+100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calculated as 1/SlewRate1-1/
SlewRate2. For example, if slew rate 1 = 1.0V/ns and slew rate 2 =0.8V/ns, then the Delta Rise/Fall Rate =-0.25ns/V.
7) Input slew rate 1.0 V/ ns.
8) Input slew rate 0.5V/ns and < 1.0V/ns.
9) Maximum burst refresh cycle : 8
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Revision 1.3
November 2009