K524G2GACB-A050 Datasheet, PDF (37/94 Pages) Samsung semiconductor – MCP MEMORY

K524G2GACB-A050
MCP MEMORY
4.2 PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte(a word) or consecutive
byte up to 2,112 bytes(1,056 Wrods), in a single page program cycle. The number of consecutive partial page programming operation within
the same page without an intervening erase operation must not exceed 4 times for a single page. The addressing should be done in sequen-
tial order in a block. A page program cycle consists of a serial data loading period in which up to 2,112 bytes(1,056 Wrods) of data may be
loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and then
serial data loading. The bytes(words) other than those to be programmed do not need to be loaded. The device supports random data input in
a page. The column address for the next data, which will be entered, may be changed to the address which follows random data input com-
mand(85h). Random data input may be operated multiple times regardless of how many times it is done in a page.
The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data
will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings necessary for
program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register com-
mand may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B
output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in
progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 9). The internal write verify detects only
errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another
valid command is written to the command register.
R/B
I/Ox
Figure 9. Program & Read Status Operation
tPROG
80h
Address & Data Input
10h
70h
Col. Add.1,2 & Row Add.1,2,3
Data
"0"
I/O0
Pass
"1"
Fail
Figure 10. Random Data Input In a Page
tPROG
R/B
I/Ox 80h
Address & Data Input 85h
Address & Data Input
10h
Col. Add.1,2 & Row Add1,2,3
Data
Col. Add.1,2
Data
"0"
70h
I/O0
Pass
"1"
Fail
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Revision 1.3
November 2009