K524G2GACB-A050 Datasheet, PDF (36/94 Pages) Samsung semiconductor – MCP MEMORY

K524G2GACB-A050
MCP MEMORY
4.0 Device Operation
4.1 PAGE READ
Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is
latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes(1,056 Wrods) of
data within the selected page are transferred to the data registers in 40µs(tR) typically. The system controller can detect the completion of this
data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 42ns
cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the
selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The col-
umn address of next data, which is going to be out, may be changed to the address which follows random data output command. Random
data output can be operated multiple times regardless of how many times it is done in a page.
CLE
CE
WE
ALE
R/B
RE
I/Ox
Figure 8. Read Operation
tR
00h
Address(5Cycle)
30h
Col. Add.1,2 & Row Add.1,2,3
Data Output(Serial Access)
Data Field
Spare Field
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Revision 1.3
November 2009