K524G2GACB-A050 Datasheet, PDF (67/94 Pages) Samsung semiconductor – MCP MEMORY

K524G2GACB-A050
MCP MEMORY
7. Burst Write Operation
The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock(CK). The address
inputs determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The first data of a burst
write cycle must be applied on the DQ pins tDS(Data-in setup time) prior to data strobe edge enabled after tDQSS from the rising edge of the
clock(CK) that the write command is issued. The remaining data inputs must be supplied on each subsequent falling and rising edge of Data
Strobe until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored.
Figure 3. Burst write operation timing
0
1
2
3
4
5
6
7
8
CK
CK
Command ^NOP
WRITEA
NOP
WRITEB
NOP
NOP
NOP
tDQSS(max)
DQS
DQs
tDQSS(max)
Hi-Z
tWPRES^tWPREH
Hi-Z
Din 0 Din 1 Din 2 Din 3 Din 0 Din 1 Din 2 Din 3
NOP
tWR
NOP
tDQSS(min)
tDQSS(min)
tWR
DQS
Hi-Z
tWPRES tWPREH
DQs
Hi-Z
Din 0 Din 1 Din 2 Din 3 Din 0 Din 1 Din 2 Din 3
tDS tDH
NOTE :
1) Burst Length=4
2) The specific requirement is that DQS be valid(High or Low) on or before this CK edge.
The case shown (DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus.
- 67 -
Revision 1.3
November 2009