K524G2GACB-A050 Datasheet, PDF (11/94 Pages) Samsung semiconductor – MCP MEMORY

K524G2GACB-A050
MCP MEMORY
Figure 1. Functional Block Diagram(x8)
VCC
VSS
A12 - A30*
X-Buffers
Latches
& Decoders
4,096M + 128M Bit for 4Gb
8,192M + 256M Bit for 8Gb DDP
NAND Flash
ARRAY
A0 - A11
Y-Buffers
Latches
& Decoders
Data Register & S/A
Y-Gating
Command
Command
Register
CE
Control Logic
RE
& High Voltage
WE
Generator
CLE ALE WP
I/O Buffers & Latches
VCC
VSS
Global Buffers
Output
Driver
I/0 0
I/0 7
Figure 2. Array Organization(x8)
1 Block = 64 Pages
(128K + 4K) Byte
4,096 blocks for 4Gb
8,192 blocks for 8Gb DDP
2K Bytes
64 Bytes
1 Page = (2K + 64)Bytes
1 Block = (2K + 64)Byte x 64 Pages
= (128K + 4K) Bytes
1 Device = (2K+64)B x 64Pages x 4,096 Blocks
= 4,224 Mbits for 4Gb
8 bit ^{1 Device = (2K+64)B x 64Pages x 8,192 Blocks}
= 8,448 Mbits for 8Gb DDP
Page Register
2K Bytes
I/O 0 ~ I/O 7
64 Bytes
Table 1. Array address : (x8)
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
1st Cycle
A0
A1
A2
A3
A4
2nd Cycle
A8
A9
A10
A11
*L
3rd Cycle
A12
A13
A14
A15
A16
4th Cycle
A20
A21
A22
A23
A24
5th Cycle
A28
A29
*A30
*L
*L
NOTE :
Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than required.
* A30 is Row address for 8G DDP.
In case of 4G Mono, A30 must be set to "Low"
I/O 5
A5
*L
A17
A25
*L
I/O 6
A6
*L
A18
A26
*L
I/O 7
A7
*L
A19
A27
*L
Address
Column Address
Column Address
Row Address
Row Address
Row Address
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Revision 1.3
November 2009