K524G2GACB-A050 Datasheet, PDF (71/94 Pages) Samsung semiconductor – MCP MEMORY

K524G2GACB-A050
MCP MEMORY
12. Write Interrupted by a Precharge & DM
A burst write operation can be interrupted by a precharge of the same bank before completion of the burst. Random column access is allowed.
A write recovery time(tWR) is required from the last data to precharge command. When precharge command is asserted, any residual data
from the burst write cycle must be masked by DM.
Figure 8. Write interrupted by a precharge and DM timing
0
1
2
3
4
5
6
7
8
CK
CK
Command
tDQSS(max)
DQS
DQs
NOP
WRITE A
NOP
NOP
NOP
NOP
PrechargeA
tDQSS(max)
tWR
Hi-Z
tWPREH
Hi-Z
tWPRES
Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7
WRITE B
NOP
tDQSS(max)
tWPREH
tWPRES
Dinb0
Dinb1
DM
tDQSS(min)
DQS
DQs
Hi-Z
Hi-Z
tDQSS(min)
tWR
tWPRES tWPREH
Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7
tDQSS(min)
tWPRES tWPREH
Dinb0 Dinb1 Dinb2
DM
NOTE :
1) Burst Length=8
Precharge timing for Write operations in Mobile DDR SDRAM requires enough time to allow ’’write recovery’’ which is the time required by a
Mobile DDR SDRAM core to properly store a full ’’0’’ or ’’1’’ level before a Precharge operation. For Mobile DDR SDRAM, a timing parameter,
tWR, is used to indicate the required amount of time between the last valid write operation and a Precharge command to the same bank.
The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is sampled by the
input clock. Inside the Mobile DDR SDRAM, the data path is eventually synchronized with the address path by switching clock domains from
the data strobe clock domain to the input clock domain. This makes the definition of when a precharge operation can be initiated after a write
very complex since the write recovery parameter must make reference to only the clock domain that affects internal write operation, i.e., the
input clock domain.
tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid data and ends on the rising clock edge that
strobes in the precharge command.
1. For the earliest possible Precharge command following a burst Write without interrupting the burst, the minimum time for write recovery is
defined by tWR.
2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the time between
the last valid write data and the rising clock edge on which the Precharge command is given. During this time, the DQS input is still
required to strobe in the state of DM. The minimum time for write recovery is defined by tWR.
3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR+tRP where tWR+tRP
starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the Bank Activate
command. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible
external Precharge command without interrupting the Write burst as described in 1 above.
4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied.
This includes Write with autoprecharge commands where tRAS(min) must still be satisfied such that a Write with autoprecharge
command has the same timing as a Write command followed by the earliest possible Precharge command which does not interrupt the
burst.
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Revision 1.3
November 2009