K524G2GACB-A050 Datasheet, PDF (51/94 Pages) Samsung semiconductor – MCP MEMORY

K524G2GACB-A050
MCP MEMORY
5. DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, Tc = -25 to 85°C)
Parameter
Symbol
Test Condition
Operating Current
(One Bank Active)
IDD0 ^{tRC=tRCmin; tCK=tCKmin; CKE is HIGH; CS is HIGH between valid commands;}
address inputs are SWITCHING; data bus inputs are STABLE
Precharge Standby Cur-
rent
in power-down mode
IDD2P ^{all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin;}
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD2PS ^{all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;}
address and control inputs are SWITCHING; data bus inputs are STABLE
Precharge Standby Cur-
rent
IDD2N ^{all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin;}
address and control inputs are SWITCHING; data bus inputs are STABLE
in non power-down mode _IDD2NS all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
Active Standby Current
in power-down mode
IDD3P ^{one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin;}
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD3PS ^{one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;}
address and control inputs are SWITCHING; data bus inputs are STABLE
Active Standby Current
IDD3N ^{one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin;}
address and control inputs are SWITCHING; data bus inputs are STABLE
in non power-down mode
(One Bank Active)
IDD3NS ^{one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;}
address and control inputs are SWITCHING; data bus inputs are STABLE
Operating Current
(Burst Mode)
IDD4R ^{one bank active; BL=4; CL=3; tCK = tCKmin; continuous read bursts; I OUT =0 mA}
address inputs are SWITCHING; 50% data change each burst transfer
IDD4W ^{one bank active; BL = 4; tCK = tCKmin ; continuous write bursts;}
address inputs are SWITCHING; 50% data change each burst transfer
Refresh Current
IDD5 ^{tRC ≥ tRFC; tCK = tCKmin ; burst refresh; CKE is HIGH;}
address and control inputs are SWITCHING; data bus inputs are STABLE
TCSR Range
Self Refresh Current
IDD6
CKE is LOW; t CK = t CKmin ;
Extended Mode Register set to all 0’s;
address and control inputs are STABLE;
data bus inputs are STABLE
Full Array
1/2 Array
1/4 Array
85°C
70°C
45°C
15°C
85°C
70°C
45°C
15°C
85°C
70°C
45°C
15°C
DDR
400
85
DDR
333
70
1.0
1.0
8
4
6
5
15
10
115
100
100
80
170
170
Values
Typ
Max
1100
1800
750
450
900
300
700
1500
500
300
750
250
500
1300
350
250
650
200
Unit Note
mA
mA
mA
mA
mA
mA
mA ¹
uA
uA
uA
NOTE :
1) IDD5 is measured in the below test condition.
Density 128Mb 256Mb 512Mb
1Gb
2Gb
Unit
tRFC
80
80
110
140
140
ns
2) IDD specifications are tested after the device is properly intialized.
3) Input slew rate is 1V/ns.
4) Definitions for IDD: LOW is defined as V IN ≤ 0.1 * VDDQ ;
HIGH is defined as V IN ≥ 0.9 * VDDQ ;
STABLE is defined as inputs stable at a HIGH or LOW level ;
SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles ;
- data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
5) DPD(Deep Power Down) function is an optional feature, and it will be enabled upon request.
Please contact Samsung for more information.
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Revision 1.3
November 2009