SH7011 Datasheet, PDF (73/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

6.3 Description of Registers
6.3.1 Interrupt Priority Registers A–H (IPRA–IPRH)
Interrupt priority registers A–H (IPRA–IPRH) are 16-bit readable/writable registers that set
priority levels from 0 to 15 for IRQ interrupts and on-chip peripheral module interrupts.
Correspondence between interrupt request sources and each of the IPRA–IPRH bits is shown in
table 6.4.
Bit: 15
14
13
12
11
10
9
8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table 6.4 Interrupt Request Sources and IPRA–IPRH
Register
Interrupt priority register A
Interrupt priority register B
Interrupt priority register C
Interrupt priority register D
Interrupt priority register E
Interrupt priority register F
Interrupt priority register G
Interrupt priority register H
15–12
IRQ0
IRQ4
Reserved
MTU0
MTU2
Reserved
A/D
TIM1, 2
Bits
11–8
7–4
IRQ1
IRQ2
IRQ5
IRQ6
Reserved Reserved
MTU0
MTU1
MTTU2
Reserved
Reserved Reserved
Reserved CMT0
Reserved Reserved
3–0
IRQ3
IRQ7
Reserved
MTU1
Reserved
SCI
CMT1
Reserved
As indicated in table 6.4, four IRQ pins or groups of 4 on-chip peripheral modules are allocated to
each register. Each of the corresponding interrupt priority ranks are established by setting a value
from H'0 (0000) to H'F (1111) in each of the four-bit groups 15–12, 11–8, 7–4 and 3–0. Interrupt
priority rank becomes level 0 (lowest) by setting H'0, and level 15 (highest) by setting H'F. 8-bit
timers 1 and 2 are set to the same priority rank.
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