SH7011 Datasheet, PDF (68/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

6.1.3 Pin Configuration
Table 6.1 shows the INTC pin configuration.
Table 6.1 Pin Configuration
Name
Non-maskable interrupt input pin
Interrupt request input pins
Abbreviation I/O
NMI
I
IRQ0–IRQ7 I
Function
Input of non-maskable interrupt
request signal
Input of maskable interrupt request
signals
6.1.4 Register Configuration
The INTC has the 10 registers shown in table 6.2. These registers set the priority of the interrupts
and control external interrupt input signal detection.
Table 6.2 Register Configuration
Name
Abbr. R/W Initial Value Address
Access Sizes
Interrupt priority register A IPRA R/W H'0000
H'FFFF8348
8, 16, 32
Interrupt priority register B IPRB R/W H'0000
H'FFFF834A
8, 16, 32
Interrupt priority register C IPRC R/W H'0000
H'FFFF834C
8, 16, 32
Interrupt priority register D IPRD R/W H'0000
H'FFFF834E
8, 16, 32
Interrupt priority register E IPRE R/W H'0000
H'FFFF8350
8, 16, 32
Interrupt priority register F IPRF R/W H'0000
H'FFFF8352
8, 16, 32
Interrupt priority register G IPRG R/W H'0000
H'FFFF8354
8, 16, 32
Interrupt priority register H
Interrupt control register
IRQ status register
IPRH
ICR
ISR
R/W H'0000
R/W ^*1
R(W)*² H'0000
H'FFFF8356
H'FFFF8358
H'FFFF835A
8, 16, 32
8, 16, 32
8, 16, 32
Notes: 1. The value when the NMI pin is high is H'8000; when the NMI pin is low, it is H'0000.
2. Only 0 can be written, in order to clear flags.
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