SH7011 Datasheet, PDF (224/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

Start transmitting
Read TDRE bit in SSR
(1)
No
TDRE = 1?
Yes
Write transmission data to TDR
and clear TDRE bit in SSR to 0
(2)
No
All data transmitted?
Yes
Read TEND bit in SSR
No
TEND = 1?
Yes
End transmission
Figure 12.4 Sample Flowchart for Transmitting Serial Data
In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0, the SCI recognizes
that the transmit data register (TDR) contains new data, and loads this data from the TDR into
the transmit shift register (TSR).
2. After loading the data from the TDR into the TSR, the SCI sets the TDRE bit to 1 and starts
transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in the SCR, the
SCI requests a transmit-data-empty interrupt (TxI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
a. Start bit: one 0 bit is output.
b. Transmit data: seven or eight bits of data are output, LSB first.
c. Parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit
is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also
be selected.
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