SH7011 Datasheet, PDF (186/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

10.4.3 Timing of Compare Match Flag Clearing
The CMF bit in the T2CSR register is cleared by reading the bit when it is set to 1, then writing 0
in it. Figure 10.5 shows the timing of CMF bit clearing by the CPU.
CK
CMF
T2CSR write cycle
T1 T2
Figure 10.5 Timing of CMF Clearing by CPU
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