SH7011 Datasheet, PDF (174/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

9.2.2 Timer 1 Control/Status Register (T1CSR)
The timer 1 control/status register (T1CSR) is an 8-bit readable/writable* register that selects the
clock to be input to the timer 1 counter (T1CNT) and the timer mode.
Bits 7, 5, and 2 through 0 are initialized to 0 by a power-on reset.
Note: The method for writing to T1CSR is different from that for general registers to prevent
inadvertent overwriting. For details, see section 9.2.3, Notes on Register Access.
Bit: 7
6
5
4
OVF
—
TME
—
Initial value: 0
0
0
1
R/W: R/(W)*
R
R/W
R
3
2
1
0
—
CKS2 CKS1 CKS0
1
0
0
0
R
R/W R/W R/W
• Bit 7—Overflow Flag (OVF): Indicates that T1CNT has overflowed from H'FF to H'00.
Bit 7: OVF
0
1
Description
No T1CNT overflow (initial value)
[Clearing condition]
Cleared by reading OVF then writing 0 in OVF
[Setting condition]
Set when T1CNT overflows
• Bit 6—Reserved: This bit always reads 0 and must only be written with 0.
• Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.
Bit 5: TME
0
1
Description
Timer disabled: T1CNT is initialized to H'00 and halted (initial value)
Timer enabled: T1CNT starts counting, and an interrupt is generated when
T1CNT overflows
• Bits 4 and 3—Reserved: These bits always read 1 and must only be written with 1.
• Bits 2 to 0—Clock Select 2 to 0 (CKS2–CKS0): These bits select one of eight internal clock
sources, obtained by dividing the system clock (φ), for input to T1CNT.
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