SH7011 Datasheet, PDF (156/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

Contention Between TGR Write and Compare Match: If a compare-match occurs in the T₂
state of the TGR write cycle, data is written to the TGR and a compare-match signal is issued
(figure 8.45).
TGR write cycle
T₁
T₂
φ
Address
TGR address
Write signal
Compare
match signal
TCNT
N
N+1
TGR
N
M
TGR write data
Figure 8.45 TGR Write and Compare Match Contention
TCNT2 Write and Overflow Contention in Cascade Connection: With timer counters TCNT1
and TCNT2 in a cascade connection, when a contention occurs during TCNT1 count (during a
TCNT2 overflow) in the T₂ state of the TCNT2 write cycle, the write to TCNT2 is conducted, and
the TCNT1 count signal is prohibited. At this point, if there is match with TGR1A and the TCNT1
value, a compare signal is issued. When the TCNT1 count clock is selected as the channel 0 input
capture source, TGR0A and TGR0C operate as input capture registers. When TGR0C compare-
match/input capture is selected as the TGR1B input capture source, TGR1B operates as an input
capture register. The timing is shown in figure 8.46.
For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT
clearing.
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