SH7011 Datasheet, PDF (177/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

9.3.2 Timing of Overflow Flag (OVF) Setting
When the timer 1 counter (T1CNT) overflows, the OVF bit is set to 1 in the timer 1 serial control
register (T1CSR) and, at the same time, an interval timer interrupt (ITI) is requested. The timing is
shown in figure 9.4.
CK
T1CNT
Overflow signal
(internal signal)
H'FF H'00
OVF
Figure 9.4 Timing of Overflow Flag (OVF) Setting
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