SH7011 Datasheet, PDF (116/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

8.2.4 Timer Interrupt Enable Register (TIER)
The TIER is an 8-bit register that controls the enable/disable of interrupt requests for each channel.
The MTU has three TIER registers, one each for channel. TIER is initialized to H'40 by a power-
on reset.
Channel 0: TIER0
Bit: 7
6
TTGE —
Initial value: 0
1
R/W: R/W
R
5
4
3
2
1
0
— TCIEV TGIED TGIEC TGIEB TGIEA
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W
Channels 1, 2: TIER1, TIER2
Bit: 7
6
TTGE —
Initial value: 0
1
R/W: R/W
R
5
4
3
— TCIEV —
0
0
0
R
R/W
R
2
1
0
— TGIEB TGIEA
0
0
0
R
R/W R/W
• Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of an
A/D conversion start request by a TGRA register input capture/compare-match.
Bit 7: TTGE
0
1
Description
Disable A/D conversion start requests generation (initial value)
Enable A/D conversion start request generation
• Bit 6—Reserved: This bit is reserved. It always reads as 1, and cannot be modified.
• Bit 5—Reserved. This bit always reads 0. The write value should always be 0.
• Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests when the
overflow flag TCFV of the timer status register (TSR) is set to 1.
Bit 4: TCIEV
0
1
Description
Disable TCFV interrupt requests (TCIV) (initial value)
Enable TCFV interrupt requests (TCIV)
107