SH7011 Datasheet, PDF (106/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

Bit 4: Bit 3:
CKEG1 CKEG0 Description
0
0
Count on rising edges (initial value)
1
Count on falling edges
1
X
Count on both rising and falling edges
Notes: 1. X: 0 or 1, don’t care.
2. Internal clock edge selection is effective when the input clock is φ/4 or slower. These
settings are ignored when φ/1, or the overflow of another channel is selected for the
input clock.
• Bits 2–0—Timer Prescaler 2–0 (TPSC2–TPSC0): TPSC2–TPSC0 select the counter clock
source for the TCNT. An independent clock source can be selected for each channel. Table 8.4
shows the possible settings for each channel.
Table 8.4 MTU Clock Sources
Internal Clock
Channel
φ/1
φ/4
φ/16 φ/64 φ/256 φ/1024
0
O
O
O
O
X
X
1
O
O
O
O
O
X
2
O
O
O
O
X
O
Note: Symbols: O: Setting possible
X: Setting not possible
Other Channel
Overflow
X
O
X
Channel 0:
Bit 2: Bit 1:
TPSC2 TPSC1
0
0
1
1
0
1
Bit 0:
TPSC0
0
1
0
1
0
1
0
1
Description
Internal clock: count with φ/1 (initial value)
Internal clock: count with φ/4
Internal clock: count with φ/16
Internal clock: count with φ/64
Reserved (Do not set)
Reserved (Do not set)
Reserved (Do not set)
Reserved (Do not set)
97