SH7011 Datasheet, PDF (178/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

9.4 Usage Notes
9.4.1 Contention between Timer 1 Counter (TCNT) Write and Increment
If a timer 1 counter clock pulse is generated during the T3 state of a timer 1 counter (TCNT) write
cycle, the data write to T1CNT takes priority and the timer counter is not incremented. Figure 9.5
shows the operation in this case.
T1CNT write cycle
T1
T2
T3
CK
Address
T1CNT address
Internal write signal
T1CNT input clock pulse
T1CNT
N
M
Counter write data
Figure 9.5 Contention between T1CNT Write and Increment
9.4.2 Rewriting Bits CKS2 to CKS0
If bits CKS2 to CKS0 in the timer 1 control/status register (T1CSR) are rewritten while 8-bit timer
1 (TIM1) is running, the timer counter may not increment correctly. TIM1 must therefore be
stopped (by clearing the TME bit to 0) before rewriting bits CKS2 to CKS0.
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