SH7011 Datasheet, PDF (175/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

Bit 2:
CKS2
Bit 1:
CKS1
Bit 0:
CKS0
Clock
Description
Overflow Period* (when φ = 20.0 MHz)
0
0
0
φ/2 (initial value) 25.6 µs
1
φ/64
819.2 µs
1
0
φ/128
1.6384 ms
1
φ/256
3.2768 ms
1
0
0
φ/512
6.5536 ms
1
φ/1024
13.1072 ms
1
0
φ/4096
52.4288 ms
1
φ/8192
104.8576 ms
Note: The overflow period is the time from when T1CNT starts counting up from H'00 until
overflow occurs.
9.2.3 Notes on Register Access
The method for writing to the timer 1 counter (T1CNT) and the timer 1 control/status register
(T1CSR) is different from that for general registers to prevent inadvertent overwriting. The
procedures for writing to and reading these registers are given below.
Writing to T1CNT and T1CSR: These registers must be written to with a word transfer
instruction. They cannot be written to with a byte instruction.
T1CNT and T1CSR both have the same write address. For a write to T1CNT, the upper byte of the
written word must contain H'5A and the lower byte must contain the write data. For a write to
T1CSR, the upper byte of the written word must contain H'A5 and the lower byte must contain the
write data. This transfers the write data from the lower byte to T1CNT or T1CSR. (See figure 9.2).
T1CNT write
15
Address: H'FFFF8610
H'5A
87
0
Write data
T1CSR write
15
Address: H'FFFF8610
H'A5
87
0
Write data
Figure 9.2 Writing to T1CNT and T1CSR
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