SH7011 Datasheet, PDF (109/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

• Bits 3–0—Modes 3–0 (MD3–MD0): These bits set the timer operation mode.
Bit 3:
MD3
0
Bit 2:
MD2
0
0
1
1
*
*: Don’t care
Bit 1:
MD1
0
1
*
*
Bit 0:
MD0
0
1
0
1
*
*
Description
Normal operation (initial value)
Reserved (do not set)
PWM mode 1
PWM mode 2
Reserved (Do not set)
Reserved (Do not set)
8.2.3 Timer I/O Control Register (TIOR)
The TIOR is a register that controls the TGR. The MTU has four TIOR registers, two for channels
0, and one each for channels 1 and 2. TIOR is initialized to H'00 by a power-on reset.
Channel 0: TIOR0H
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
IOA3 IOA2 IOA1 IOA0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R/W R/W R/W R/W
Channels 1, 2: TIOR1, TIOR2
Bit:
Initial value:
R/W:
7
IOB3
0
R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
0
IOA0
0
R/W
Bits 7–4—I/O Control B3–B0 (IOB3–IOB0): These bits set the TGRB register function.
(TIOR1 and TIOR2 only. TIOR0H is a reserved bit: it always reads 0 and its write value should
always be 0.)
Bits 3–0—I/O Control A3–B0 (IOA3–IOA0): These bits set the TGRA register function.
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