SH7011 Datasheet, PDF (168/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

(7) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is
Restarted in Normal Mode: Figure 8.55 shows an explanatory diagram of the case where an
error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting.
MTU output
TIOC*A
1
2
3
RESET TMDR TIOR
(PWM2) (1 init
0 out)
4
PFC
(MTU)
5
TSTR
(1)
6
Match
7
8
9
10 11
Error PFC TSTR TMDR TIOR
occurs (PORT) (0) (normal) (1 init
0 out)
• Not initialized (cycle register)
12
PFC
(MTU)
13
TSTR
(1)
TIOC*B
Port output
PEn
Z
PEn
Z
n = 0, 2, 4–7, 12–14
Figure 8.55 Error Occurrence in PWM Mode 2, Recovery in Normal Mode
1. After a reset, MTU output is low and ports are in the high-impedance state.
2. Set PWM mode 2.
3. Initialize the pins with TIOR. (The example shows initial high output, with low output on
compare-match occurrence. In PWM mode 2, the cycle register pins are not initialized. In the
example, TIOC*A is the cycle register.)
4. Set MTU output with the PFC.
5. The count operation is started by TSTR.
6. Output goes low on compare-match occurrence.
7. An error occurs.
8. Set port output with the PFC and output the inverse of the active level.
9. The count operation is stopped by TSTR.
10. Set normal mode.
11. Initialize the pins with TIOR.
12. Set MTU output with the PFC.
13. Operation is restarted by TSTR.
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