SH7011 Datasheet, PDF (118/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

8.2.5 Timer Status Register (TSR)
The timer status register (TSR) is an 8-bit register that indicates the status of each channel. The
MTU has three TSR registers, one each for channel. TSR is initialized to H'C0 by a power-on
reset.
Channel 0: TSR0
Bit: 7
6
5
4
—
—
—
TCFV
Initial value: 1
1
0
0
R/W: R
R
R R/(W)*
Note: Only 0 writes to clear the flags are possible.
3
TGFD
0
R/(W)*
2
TGFC
0
R/(W)*
1
TGFB
0
R/(W)*
0
TGFA
0
R/(W)*
Channels 1, 2: TSR1, TSR2
Bit: 7
6
5
4
3
—
—
—
TCFV
—
Initial value: 1
1
0
0
0
R/W: R
R
R
R/(W)*
R
Note: Only 0 writes to clear the flags are possible.
2
1
0
—
TGFB TGFA
0
0
0
R R/(W)* R/(W)*
• Bits 7 and 6—Reserved. These bits always read 1. The write value should always be 1.
• Bit 5—Reserved. This bit always reads 0. The write value should always be 0.
• Bit 4—Overflow Flag (TCFV): This status flag indicates the occurrence of a TCNT counter
overflow.
Bit 4: TCFV
0
1
Description
Clear condition: With TCFV =1, a 0 write to TCFV after reading it
(initial value)
Set condition: When the TCNT value overflows (H'FFFF → H'0000)
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