SH7011 Datasheet, PDF (273/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

17.3.2 Control Signal Timing
Table 17.5 Control Signal Timing (Conditions: V_CC = 3.0 to 3.6V, AV_CC = 3.0 to 5.5V,
AV_CC V _CC, V_SS = AV_SS = 0V, T_a = Ð20 to +75°C)
Item
Symbol Min
Max
Unit
Figure
RES rise/fall
RES pulse width
t , _RESr t_RESf —
t _RESW
40
200
ns
—
t _cyc
17.4
NMI rise/fall
RES setup time *
t , _NMIr t_NMIf —
200
ns
t _RESS
100
—
ns
17.5
17.4
NMI setup time (during edge detection)
t _NMIS
100
—
ns
17.5
IRQ7–IRQ0 setup time (edge detection)
t _IRQES
100
—
ns
IRQ7–IRQ0 setup time (level detection)
t _IRQLS
100
—
ns
NMI hold time
t _NMIH
50
—
ns
17.5
IRQ7–IRQ0 hold time
t _IRQEH
50
—
ns
Note: The RES, NMI, and IRQ7–IRQ0 signals are asynchronous inputs, but when the setup times
shown here are provided, the signals are considered to have produced changes at clock
rise (for RES) or clock fall (for NMI and IRQ7–IRQ0). If the setup times are not provided,
recognition is delayed until the next clock rise or fall.
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