SH7011 Datasheet, PDF (101/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

8.1.2 Block Diagram
Figure 8.1 is the block diagram of the MTU.
[Clock input]
Internal clock:
φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
[I/O pins]
Channel 0:
TIOC0A
TIOC0C
Channel 1:
TIOC1A
TIOC1B
Channel 2:
TIOC2A
TIOC2B
Figure 8.1 MTU Block Diagram
Internal data bus
A/D conversion
start request signal
[Interrupt request
signal]
Channel 0:
TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
Channel 1:
TGI1A
TGI1B
TCI1V
Channel 2:
TGI2A
TGI2B
TCI2V
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