SH7011 Datasheet, PDF (60/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

5.4 Interrupts
Table 5.7 shows the sources that start up interrupt exception processing. These are divided into
NMI, IRQ and on-chip peripheral modules.
Table 5.7 Interrupt Sources
Type
NMI
IRQ
On-chip peripheral module
Request Source
NMI pin (external input)
IRQ0–IRQ7 (external input)
Multifunction timer/pulse unit (MTU)
Serial communications interface (SCI)
A/D converter
Compare match timer (CMT)
8-bit timer 1
8-bit timer 2
Number of
Sources
1
8
11
4
1
2
1
1
Each interrupt source is allocated a different vector number and vector table offset. See section 6,
Interrupt Controller, table 6.3, Interrupt Exception Processing Vectors and Priorities, for more
information on vector numbers and vector table address offsets.
5.4.1 Interrupt Priority Level
The interrupt priority order is predetermined. When multiple interrupts occur simultaneously
(overlap), the interrupt controller (INTC) determines their relative priorities and starts up
processing according to the results.
The priority order of interrupts is expressed as priority levels 0–16, with priority 0 the lowest and
priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always
accepted. The user break interrupt priority level is 15. IRQ interrupts and on-chip peripheral
module interrupt priority levels can be set freely using the INTC’s interrupt priority level setting
registers A through H (IPRA to IPRH) as shown in table 5.8. The priority levels that can be set are
0–15. Level 16 cannot be set. See section 6.3.1, Interrupt Priority Registers A-H (IPRA-IPRH), for
more information on IPRA to IPRH.
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