SH7011 Datasheet, PDF (12/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

Section 1 SH7011 Overview
1.1 SH7011 Overview
The SH7011 CMOS single-chip microprocessors integrate a Hitachi-original architecture, high-
speed CPU with peripheral functions required for system configuration.
The CPU has a RISC-type instruction set. Most instructions can be executed in one clock cycle,
which greatly improves instruction execution speed. In addition, the 32-bit internal-bus
architecture enhances data processing power. With this CPU, it has become possible to assemble
low cost, high performance/high-functioning systems, even for applications that were previously
impossible with microprocessors, such as real-time control, which demands high speeds.
In addition, the SH7011 includes on-chip peripheral functions necessary for system configuration,
such as large-capacity ROM, timers, a serial communication interface (SCI), an A/D converter, an
interrupt controller, and I/O ports. Memory or peripheral LSIs can be connected efficiently with an
external memory access support function. This greatly reduces system cost.
1.1.1 SH7011 Features
CPU:
• Original Hitachi architecture
• 32-bit internal data bus
• General-register machine
 Sixteen 32-bit general registers
 Three 32-bit control registers
 Four 32-bit system registers
• RISC-type instruction set
 Instruction length: 16-bit fixed length for improved code efficiency
 Load-store architecture (basic operations are executed between registers)
 Delayed branch instructions reduce pipeline disruption during branch
 Instruction set based on C language
• Instruction execution time: one instruction/cycle (50 ns/instruction at 20-MHz operation)
• Address space: Architecture supports 4 Gbytes
• On-chip multiplier: multiplication operations (32 bits × 32 bits → 64 bits) and
multiplication/accumulation operations (32 bits × 32 bits + 64 bits → 64 bits) executed in two
to four cycles
• Five-stage pipeline
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