SH7011 Datasheet, PDF (121/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

8.2.7 Timer General Register (TGR)
Each timer general register (TGR) is a 16-bit register that can function as either an output compare
register or an input capture register. There are a total of eight TGR, four each for channels 0 and
two each for channels 1 and 2. The TGRC and TGRD of channels 0 can be set to operate as buffer
registers. The TGR register and buffer register combinations are TGRA with TGRC, and TGRB
with TGRD.
The TGRs are initialized to H'FFFF by a power-on reset. Accessing of the TGRs in 8-bit units is
disabled; they may only be accessed in 16-bit units.
Bit: 15
14
13
12
11
10
9
8
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
8.2.8 Timer Start Register (TSTR)
The timer start register (TSTR) is an 8-bit read/write register that starts and stops the timer
counters (TCNT) of channels 0–2. TSTR is initialized to H'00 upon power-on reset.
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
CST2 CST1 CST0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W R/W R/W
• Bits 7–3—Reserved. These bits always read 0. The write value should always be 0.
• Bits 2–0—Counter Start 2-0 (CST2-CST0): Select starting and stopping of the timer counters
(TCNT). The corresponding between bits and channels is as follows:
CST2: Channel 2 (TCNT2)
CST1: Channel 1 (TCNT1)
CST0: Channel 0 (TCNT0)
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