SH7011 Datasheet, PDF (155/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

Contention between Buffer Register Write and Input Capture: If an input capture signal is
issued in the T₂ state of the buffer write cycle, write to the buffer register does not occur, and
buffer operation takes priority (figure 8.44).
φ
Address
Write signal
Input capture
signal
TCNT
Buffer register write cycle
T₁
T₂
Buffer register
address
N
TGR
M
N
Buffer
register
M
Figure 8.44 Buffer Register Write and Input Capture Contention
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