SH7011 Datasheet, PDF (10/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

12.2.6 Serial Control Register (SCR).............................................................................. 197
12.2.7 Serial Status Register (SSR)................................................................................. 199
12.2.8 Bit Rate Register (BRR)....................................................................................... 203
12.3 Operation ........................................................................................................................... 211
12.3.1 Overview .............................................................................................................. 211
12.3.2 Operation in Asynchronous Mode........................................................................ 212
12.3.3 Multiprocessor Communication ........................................................................... 221
12.4 Interrupt ............................................................................................................................. 228
12.5 Notes on Use...................................................................................................................... 229
Section 13 A/D Converter (A/D)..................................................................................... 231
13.1 Overview............................................................................................................................ 231
13.1.1 Features ................................................................................................................ 231
13.1.2 Block Diagram...................................................................................................... 232
13.1.3 Pin Configuration ................................................................................................. 233
13.1.4 Register Configuration ......................................................................................... 234
13.2 Register Descriptions......................................................................................................... 234
13.2.1 A/D Data Registers A–D (ADDRA–ADDRD).................................................... 234
13.2.2 A/D Control/Status Register (ADCSR)................................................................ 235
13.2.3 A/D Control Register (ADCR)............................................................................. 237
13.3 CPU Interface .................................................................................................................... 238
13.4 Operation ........................................................................................................................... 240
13.4.1 Single Mode (SCAN = 0) ..................................................................................... 240
13.4.2 Scan Mode (SCAN = 1) ....................................................................................... 242
13.4.3 Input Sampling and A/D Conversion Time.......................................................... 244
13.4.4 MTU Trigger Input Timing.................................................................................. 246
13.5 A/D Conversion Precision Definitions.............................................................................. 246
13.6 Notes on Use...................................................................................................................... 248
13.6.1 Analog Voltage Settings....................................................................................... 248
13.6.2 Handling of Analog Input Pins............................................................................. 248
Section 14 Pin Function Controller ................................................................................ 251
14.1 Overview............................................................................................................................ 251
14.2 Register Configuration ...................................................................................................... 251
14.3 Register Descriptions......................................................................................................... 252
14.3.1 Port A I/O Register H (PAIORH) ........................................................................ 252
14.3.2 Port E I/O Register (PEIOR)................................................................................ 252
14.3.3 Port E Control Register 2 (PECR2)...................................................................... 253
Section 15 I/O Ports (I/O).................................................................................................. 255
15.1 Overview............................................................................................................................ 255
15.2 Port A................................................................................................................................. 255
15.2.1 Register Configuration ......................................................................................... 255
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