SH7011 Datasheet, PDF (207/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

• Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted.
Bit 2: TEIE
Description
0
Transmit-end interrupt (TEI) requests are disabled* (initial value)
1
Transmit-end interrupt (TEI) requests are enabled.*
Note: The TEI request can be cleared by reading the TDRE bit in the serial status register (SSR)
after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end (TEND) bit
to 0; or by clearing the TEIE bit to 0.
• Bits 1 and 0—Reserved. These bits always read 0. The write value should always be 0.
12.2.7 Serial Status Register (SSR)
The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status
flags that indicate SCI operating status.
The CPU can always read and write the SSR, but cannot write 1 in the status flags (TDRE, RDRF,
ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after
being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. The SSR is
initialized to H'84 by a power-on reset.
Bit: 7
6
5
4
3
TDRE RDRF ORER FER PER
Initial value: 1
0
0
0
0
R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note: The only value that can be written is a 0 to clear the flag.
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
• Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from the TDR into the TSR and new serial transmit data can be written in the TDR.
Bit 7: TDRE
0
1
Description
TDR contains valid transmit data
TDRE is cleared to 0 when software reads TDRE after it has been set to 1, then
writes 0 in TDRE
TDR does not contain valid transmit data (initial value)
TDRE is set to 1 when the chip is power-on reset the TE bit in the serial control
register (SCR) is cleared to 0, or TDR contents are loaded into TSR, so new data
can be written in TDR
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