SH7011 Datasheet, PDF (232/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data
from the TDR into the TSR, outputs the stop bit, then begins serial transmission of the next
frame. If TDRE is 1, the SCI sets the TEND bit in the SSR to 1, outputs the stop bit, then
continues output of 1 bits in the marking state. If the transmit-end interrupt enable bit (TEIE)
in the SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time.
Figure 12.10 shows an example of SCI receive operation in the multiprocessor format.
1
Serial
data
TDRE
Start
bit
0 D0
Multiprocessor
bit
Stop Start
Data
bit bit
D1 D7 0/1 1 0 D0
Multiprocessor
bit
Stop
Data
bit
1
D1
D7 0/1 1
Idle
(marking
state)
TEND
TxI
interrupt
request
TxI interrupt
handler writes
data in TDR and
clears TDRE to 0
TxI
interrupt
request
TEI
interrupt
request
1 frame
Figure 12.10 SCI Multiprocessor Transmit Operation (8-Bit Data with Multiprocessor Bit
and One Stop Bit)
Receiving Multiprocessor Serial Data: Figure 12.11 shows a sample flowchart for receiving
multiprocessor serial data. The procedure for receiving multiprocessor serial data is listed below.
1. ID receive cycle: Set the MPIE bit in the serial control register (SCR) to 1.
2. SCI status check and compare to ID reception: Read the serial status register (SSR), check that
RDRF is set to 1, then read data from the receive data register (RDR) and compare with the
processor’s own ID. If the ID does not match the receive data, set MPIE to 1 again and clear
RDRF to 0. If the ID matches the receive data, clear RDRF to 0.
3. Receive error handling and break detection: If a receive error occurs, read the ORER and FER
bits in SSR to identify the error. After executing the necessary error processing, clear both
ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a
framing error occurs, the RxD pin can be read to detect the break state.
4. SCI status check and data receiving: Read SSR, check that RDRF is set to 1, then read data
from the receive data register (RDR).
224