SH7011 Datasheet, PDF (69/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

6.2 Interrupt Sources
There are four types of interrupt sources: NMI, user breaks, IRQ, and on-chip peripheral modules.
Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the
highest). Giving an interrupt a priority level of 0 masks it.
6.2.1 NMI Interrupts
The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin is detected by
edge. Use the NMI edge select bit (NMIE) in the interrupt control register (ICR) to select either
the rising or falling edge. NMI interrupt exception processing sets the interrupt mask level bits
(I3–I0) in the status register (SR) to level 15.
6.2.2 IRQ Interrupts
IRQ interrupts are requested by input from pins IRQ0–IRQ7. Set the IRQ sense select bits
(IRQ0S–IRQ7S) of the interrupt control register (ICR) to select low level detection or falling edge
detection for each pin. The priority level can be set from 0 to 15 for each pin using the interrupt
priority registers A and B (IPRA–IPRB).
When IRQ interrupts are set to low level detection, an interrupt request signal is sent to the INTC
during the period the IRQ pin is low level. Interrupt request signals are not sent to the INTC when
the IRQ pin becomes high level. Interrupt request levels can be confirmed by reading the IRQ
flags (IRQ0F–IRQ7F) of the IRQ status register (ISR).
When IRQ interrupts are set to falling edge detection, interrupt request signals are sent to the
INTC upon detecting a change on the IRQ pin from high to low level. IRQ interrupt request
detection results are maintained until the interrupt request is accepted. Confirmation that IRQ
interrupt requests have been detected is possible by reading the IRQ flags (IRQ0F–IRQ7F) of the
IRQ status register (ISR), and by writing a 0 after reading a 1, IRQ interrupt request detection
results can be withdrawn.
In IRQ interrupt exception processing, the interrupt mask bits (I3–I0) of the status register (SR)
are set to the priority level value of the accepted IRQ interrupt.
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