SH7011 Datasheet, PDF (143/292 Pages) Renesas Technology Corp – CMOS single-chip microprocessors

Table 8.8 MTU Interrupt Sources
Channel
Interrupt Source Description
Priority*
0
TGI0A
TGR0A input capture/compare-match High
TGI0B
TGR0B input capture/compare-match
TGI0C
TGR0C input capture/compare-match
TGI0D
TGR0D input capture/compare-match
TCI0V
TCNT0 overflow
1
TGI1A
TGR1A input capture/compare-match
TGI1B
TGR1B input capture/compare-match
TCI1V
TCNT1 overflow
2
TGI2A
TGR2A input capture/compare-match
TGI2B
TGR2B input capture/compare-match
TCI2V
TCNT2 overflow
TCI2U
TCNT2 underflow
Low
Note: Indicates the initial status following reset. The ranking of channels can be altered using the
interrupt controller.
8.5.2 A/D Converter Activation
The TGRA register input capture/compare-match of any channel can be used to activate the on-
chip A/D converter.
If the TTGE bit of the TIER is already set to 1 when the TGFA flag in the TSR is set to 1 by a
TGRA register input capture/compare-match of any of the channels, an A/D conversion start
request is sent to the A/D converter. If the MTU conversion start trigger is selected at such a time
on the A/D converter side when this happens, the A/D conversion starts.
The MTU has 3 TGRA register input capture/compare-match interrupts, one for each channel, that
can be used as A/D converter activation sources.
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