M16C26 Datasheet, PDF (69/239 Pages) Renesas Technology Corp – 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES

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Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
Precautions for Interrupts
M16C/26 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• When the polarity of the INT0 , INT1, INT3 through INT5 pins is changed, the interrupt request bit is
sometimes set to “1”. After changing the polarity, set the interrupt request bit to “0”. Figure 1.9.13
shows the procedure for changing the INT interrupt generate factor.
(5) Watchdog timer interrupt
• Write to the watchdog timer start register after the watchdog timer interrupt occurs (initialize watchdog
timer).
(6) Rewrite the interrupt control register
Example 1:
INT_SWITCH1:
FCLR I
AND.B #00h, 0055h
NOP
NOP
FSET I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR I
AND.B #00h, 0055h
MOV.W MEM, R0
FSET I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Dummy read.
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
FCLR I
AND.B #00h, 0055h
POPC FLG
; Push Flag register onto stack
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
• To rewrite the interrupt control register, do so at a point where an interrupt request for that register is not
generated. If there is possibility of the interrupt request occur, disable the interrupt before rewriting the
interrupt control register. Some program examples are described as follow:
When changing an interrupt control register with interrupts enabled, please read the following precau-
tions on instructions used before changing the register.
(1) Changing a non-interrupt request bit
If an interrupt request for an interrupt control register is generated during an instruction to rewrite the
register is being executed, there is a case that the interrupt request bit is not set and consequently the
interrupt is ignored. This will depend on the instruction. If this creates problems, use the instructions
below to change the register.
Instructions : AND, OR, BCLR, BSET
(2) Changing the interrupt request bit
When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit
is not cleared sometimes. This will depend on the instruction. If this creates problems, use the instruc-
tions below to change the register.
Instructions : MOV
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