M16C26 Datasheet, PDF (48/239 Pages) Renesas Technology Corp – 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES

Udenvdeelropment
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative
Power Control
and
subject to change.
SINGLE-CHIP 16-BIT
M16C/26 Group
CMOS MICROCOMPUTER
Transition of stop mode, wait mode
Reset
All oscillators stopped
Stop mode
CM10=1
Interrupt
Interrupt
All oscillators stopped
Stop mode
CM10=1
All oscillators stopped CM10=1
Stop mode
Interrupt
Stop mode
CM10=1
Interrupt
(Note 2)
Medium-speed mode
(divided-by-8 mode)
WAIT
instruction
Interrupt
CPU operation stopped
Wait mode
When
low power
dissipation
mode
High-speed/medium-
speed mode
When
low-speed
mode
Low-speed/low power
dissipation mode
WAIT
instruction
Interrupt
WAIT
instruction
(Note 1)
Interrupt
Wait mode
Wait mode
Ring oscillator, Ring oscillator
dissipation mode
WAIT
instruction
(Note 1)
Interrupt
Wait mode
Normal mode
(Refer to the following for the transition of normal mode.)
Transition of normal mode
CM06 = 1
Main clock is oscillating
Sub clock is oscillating
High-speed mode
BCLK : f(XIN)
CM07 = 0 CM06 = 0
CM17 = 0 CM16 = 0
Medium-speed mode
(divided-by-4 mode)
Main clock is oscillating
Sub clock is stopped
Medium-speed mode
(divided-by-8 mode)
BCLK : f(XIN)/8
CM07 = 0 CM06 = 1
CM04 = 0
CM04 = 1
(Notes 3, 5)
CM07 = 0 (Note 3)
CM06 = 1
CM04 = 0
Medium-speed mode
(divided-by-2 mode)
BCLK : f(XIN)/2
CM07 = 0 CM06 = 0
CM17 = 0 CM16 = 1
Medium-speed mode
(divided-by-16 mode)
Medium-speed mode
(divided-by-8 mode)
BCLK : f(XIN)/8
CM07 = 0
CM06 = 1
CM07 = 0
(Note 3, 5)
CM07 = 1
(Note 4)
Main clock is oscillating
Sub clock is oscillating
Low-speed mode
BCLK : f(XCIN)
CM07 = 1
BCLK : f(XIN)/4
CM07 = 0 CM06 = 0
CM17 = 1 CM16 = 0
BCLK : f(XIN)/16
CM07 = 0 CM06 = 0
CM17 = 1 CM16 = 1
CM04 = 0
CM04 = 1
Main clock is oscillating
Sub clock is stopped
CM05 = 0
CM05 = 1
Main clock is stopped
Sub clock is oscillating
CM07 = 1 (Note 4)
CM05 = 1
Low power
dissipation mode
BCLK : f(XCIN)
CM07 = 1 , CM06 = 1
CM15 = 1
High-speed mode
BCLK : f(XIN)
CM07 = 0 CM06 = 0
CM17 = 0 CM16 = 0
Medium-speed mode
(divided-by-2 mode)
BCLK : f(XIN)/2
CM07 = 0 CM06 = 0
CM17 = 0 CM16 = 1
CM07 = 0 (Note 3)
CM06 = 0 (Note 5)
CM04 = 1
CM06 = 0
(Notes 3, 5)
Medium-speed mode
(divided-by-4 mode)
Medium-speed mode
(divided-by-16 mode)
BCLK : f(XIN)/4
CM07 = 0 CM06 = 0
CM17 = 1 CM16 = 0
BCLK : f(XIN)/16
CM07 = 0 CM06 = 0
CM17 = 1 CM16 = 1
CM03="1"
Note 1: When bit PM21 = "0" (system clock protective function unused).
Note 2: The ring oscillator clock divided by 8 provides BCLK.
Note 3: Switch clock after oscillation of main clock is sufficiently stable.
Note 4: Switch clock after oscillation of sub clock is sufficiently stable.
Note 5: Change CM06 after changing CM17 and CM16.
Figure 1.8.8. State transition diagram of power control mode
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Renesas Technology Corp.