M16C26 Datasheet, PDF (144/239 Pages) Renesas Technology Corp – 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES

Udenvdeelropment
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative
Clock Asynchronous Serial I/O (UART) Mode
and
subject to change.
SINGLE-CHIP 16-BIT
M16C/26 Group
CMOS MICROCOMPUTER
Tc
Transfer clock
Transmit enable
1
bit(TE)
0
Transmit buffer
1
empty flag(TI)
0
TxD2
RxD2
Signal conductor level
(Note)
Transmit register 1
empty flag (TXEPT) ₀
Transmit interrupt ¹
request bit (IR)
0
Data is set in UART2 transmit buffer register
Start
bit
Transferred from UART2 transmit buffer register to UART2 transmit register
Parity Stop
bit
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
An L level returns from TxD2 due to
the occurrence of a parity error.
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
The level is detected by the
interrupt routine.
The level is
detected by the
interrupt routine.
Shown in ( ) are bit symbols.
Cleared to 0 when interrupt request is accepted, or cleared by software
The above timing applies to the following settings :
* Parity is enabled.
* One stop bit.
* Transmit interrupt cause select bit = 1 .
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f1SIO, f2SIO, f8SIO, f32SIO)
n : value set to BRG2
Note : Equal in waveform because TxD2 and RxD2 are connected.
Tc
Transfer clock
Receive enable
1
bit (RE)
0
RxD2
TxD2
Signal conductor level
(Note)
Receive complete 1
flag (RI)
0
Receive interrupt ¹
request bit (IR)
0
Start
bit
Parity Stop
bit
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P
SP
An L level returns from TxD2 due to
the occurrence of a parity error.
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Read to receive buffer
Read to receive buffer
Cleared to 0 when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
* Parity is enabled.
* One stop bit.
* Transmit interrupt cause select bit = 0 .
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f1SIO, f2SIO, f8SIO, f32SIO)
n : value set to BRG2
Note : Equal in waveform because TxD2 and RxD2 are connected.
Figure 1.15.24. Typical transmit/receive timing in UART mode (used for SIM interface)
138
Renesas Technology Corp.