M16C26 Datasheet, PDF (125/239 Pages) Renesas Technology Corp – 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES

Udenvdeelropment
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative
Clock Synchronous Serial I/O Mode
and
subject to change.
SINGLE-CHIP 16-BIT
M16C/26 Group
CMOS MICROCOMPUTER
Clock Synchronous Serial I/O Mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.15.2
and 1.15.3 list the specifications of the clock synchronous serial I/O mode. Figure 1.15.11 shows the
UARTi transmit/receive mode register.
Table 1.15.2. Specifications of clock synchronous serial I/O mode (1)
Item
Transfer data format
Transfer clock
037816
Transmission/reception control
Transmission start condition
Reception start condition
Interrupt request
generation timing
UARTi
Error detection
Specification
• Transfer data length: 8 bits
• When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816
= “0”) : fi/ 2(n+1) (Note 1) fi = f1SIO, f2SIO, f8SIO, f32SIO
• When external clock is selected (bit 3 at addresses 03A016, 03A816,
= “1”) : Input from CLKi pin
• CTS function, RTS function, CTS and RTS function disabled: selectable
• To start transmission, the following requirements must be met:
_ _{Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”}
_ _{Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”}
_ _{When CTS function selected, CTS input level = “L”}
• Furthermore, if external clock is selected, the following requirements must also be met:
_ _{CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”:}
CLKi input level = “H”
_ _{CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”:}
CLKi input level = “L”
• To start reception, the following requirements must be met:
_ _{Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1”}
_ _{Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”}
_ _{Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”}
• Furthermore, if external clock is selected, the following requirements must
also be met:
_ _{CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”:}
CLKi input level = “H”
_ _{CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”:}
CLKi input level = “L”
• When transmitting
_ _{Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at}
address 037D16) = “0”: Interrupts requested when data transfer from
transfer buffer register to UARTi transmit register is completed
_ _{Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at}
address 037D16) = “1”: Interrupts requested when data transmission from
UARTi transfer register is completed
• When receiving
_ _{Interrupts requested when data transfer from UARTi receive register to}
UARTi receive buffer register is completed
• Overrun error (Note 2)
Generated 7 clock periods after the device started receiving the next data
before reading out the contents of the UARTi receive buffer register.
Note 1: “n” denotes the value 0016 to FF16 that is set in the UART bit rate generator.
Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. In addition,
the UARTi receive interrupt request bit does not change.
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