M16C26 Datasheet, PDF (149/239 Pages) Renesas Technology Corp – 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES

Udenvdeelropment
Preliminary Specifications Rev.
Specifications in this manual are
UART2 Special Mode Register
0.9
tentative
and
subject to change.
SINGLE-CHIP 16-BIT
M16C/26 Group
CMOS MICROCOMPUTER
Setting “1” in the I2C mode select bit (IICM) causes ports to work as data transmission-reception terminal
SDAi, clock input-output terminal SCLi, and port respectively. A delay circuit is added to the SDA2 trans-
mission output, so the SDA2 output changes after SCL2 fully goes to “L”.
An attempt to read Port (SCL2) results in getting the terminal’s level regardless of the content of the port
direction register. The initial value of SDA2 transmission output in this mode goes to the value set in port.
The interrupt factors of the bus collision detection interrupt, UART2 transmission interrupt, and of UART2
reception interrupt turn to the start/stop condition detection interrupt, acknowledgment non-detection
interrupt, and acknowledgment detection interrupt respectively.
The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA2
terminal is detected with the SCL2 terminal staying “H”. The stop condition detection interrupt refers to
the interrupt that occurs when the rising edge of the SDA2 terminal is detected with the SCL2 terminal
staying “H”. The bus busy flag (bit 2 of the UART2 special mode register) is set to “1” by the start condition
detection, and set to “0” by the stop condition detection.
The acknowledgment non-detection interrupt refers to the interrupt that occurs when the SDA2 terminal
level is detected still staying “H” at the rising edge of the 9th transmission clock. The acknowledgment
detection interrupt refers to the interrupt that occurs when SDA2 terminal’s level is detected already went
to “L” at the 9th transmission clock. Also, assigning (UART2 reception) to the DMA1 request factor select
bits provides the means to start up the DMA transfer by the effect of acknowledgment detection.
Bit 1 of the UART2 special mode register is used as the arbitration lost detecting flag control bit. Arbitra-
tion means the act of detecting the nonconformity between transmission data and SDA2 terminal data at
the timing of the SCL2 rising edge. This detecting flag is located at bit 11 of the UART2 reception buffer
register, and “1” is set in this flag when nonconformity is detected. Use the arbitration lost detecting flag
control bit to choose which way to use to update the flag, bit by bit or byte by byte. When setting this bit to
“1” and updated the flag byte by byte if nonconformity is detected, the arbitration lost detecting flag is set
to “1” at the falling edge of the 9th transmission clock.
If update the flag byte by byte, must judge and clear (“0”) the arbitration lost detecting flag after complet-
ing the first byte acknowledge detect and before starting the next one byte transmission.
Bit 3 of the UART2 special mode register is used as SCL2- and L-synchronous output enable bit. Setting
this bit to “1” goes the port data register to “0” in synchronization with the SCL2 terminal level going to “L”.
Renesas Technology Corp.
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