M16C26 Datasheet, PDF (177/239 Pages) Renesas Technology Corp – 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES

Udenvdeelropment
Preliminary Specifications Rev.
Specifications in this manual are
Electrical Characteristics
0.9
tentative
and
subject to change.
SINGLE-CHIP 16-BIT
M16C/26 Group
CMOS MICROCOMPUTER
Electrical Characteristics
Table 1.18.1. Absolute maximum ratings
Symbol
VCC
Supply voltage
Parameter
AVCC
VI
Analog supply voltage
Input
voltage
P15 to P17, P60 to P67, P72 to P77,
P80 to P83,P85 to P87, P90 to P93,
P100 to P107, XIN, VREF, RESET, CNVSS
Condition
VCC=AVCC
VCC=AVCC
Rated Value
-0.3 to 6.5
-0.3 to 6.5
-0.3 to VCC+0.3
Unit
V
V
V
P70, P71
Output
P15 to P17, P60 to P67, P72 to P77,
voltage
P80 to P83, P85 to P87, P90 to P93,
P100 to P107, XOUT
VO
-0.3 to 6.5
V
-0.3 to VCC+0.3
V
P70, P71
Pd
Power dissipation
Topr
Operating ambient temperature
Tstg
Storage temperature
Note : Specify a product of -40°C to 85°C to use it.
Topr=25 C
-0.3 to 6.5
V
300
mW
-20 to 85 / -40 to 85 (Note)
C
-65 to 150
C
Tables 1.18.2a. & 1.18.2b. Electrical Characteristics for Flash ROM E/W Cycles
Table 1.18.2a. Characteristics (Note 1) for 100 E/W cycle products (D3, D5, U3, U5)
Symbol
Parameter
Standard value
Min.
Typ.
(Note 2)
–
–
–
td(SR-ES)
–
Erase/Write cycle (Note 3)
Word write time
Block erase time
2Kbyte block
8Kbyte block
16Kbyte block
32Kbyte block
Time delay from Suspend Request until Erase Suspend
Data retention time (Note 5)
100 (Note 4)
75
0.2
0.4
0.7
1.2
10
Max.
600
9
9
9
9
20
Unit
cycle
µs
s
s
s
s
ms
year
Table 1.18.2b. Characteristics (Note 6) for 10000 E/W cycle products (D7, D9, U7, U9) [Block A and Block B (Note 7)]
Symbol
Parameter
–
–
–
td(SR-ES)
Erase/Write cycle (Notes 3, 8, 9)
Word write time
Block erase time (2Kbyte block)
Time delay from Suspend Request until Erase Suspend
Standard value
Min.
Typ.
(Note 2)
Max.
10000 (Notes 4, 10)
100
0.3
20
Unit
cycle
µs
s
ms
Note 1: When not otherwise specified, Vcc = 2.7-5.5V; Topr = 0-60 C.
Note 2: Vcc=5.0V; Topr = 25 C.
Note 3: Definition of E/W cycle: Each block may be written to a variable number of times - up to a maximum of the total number of
distinct word addresses - for every block erase. Performing multiple writes to the same address before an erase operation is
prohibited.
Note 4: Maximum number of E/W cycles for which operation is guaranteed.
Note 5: Topr = -40-85 C (D3, D7, U3, U7) / -20-85 C (D5, D9, U5, U9).
Note 6: When not otherwise specified, Vcc = 2.7-5.5V; Topr = -20-85 C (D9, U9) / -40-85 C (D7, U7).
Note 7: Table 1.18.2b applies for Block A or B E/W cycles > 1000. Otherwise, use Table 1.18.2a.
Note 8: To reduce the number of E/W cycles, a block erase should ideally be performed after writing as many different word
addresses (only one time each) as possible. It is important to track the total number of block erases.
Note 9: Should erase error occur during block erase, attempt to execute clear status register command, then block erase
command at least three times until erase error disappears.
Note 10: When Block A or B E/W cycles exceed 100 (D7, D9, U7, U9), select one wait state per block access. When
FMR17 is set to "1", one wait state is inserted per access to Block A or B - regardless of the value of PM17.
Wait state insertion during access to all other blocks, as well as to internal RAM, is controlled by PM17 -
regardless of the setting of FMR17.
Note 11: Customers desiring E/W failure rate information should contact their Renesas technical support representative.
Renesas Technology Corp.
171