M16C26 Datasheet, PDF (119/239 Pages) Renesas Technology Corp – 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES

Udenvdeelropment
Serial I/O
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
M16C/26 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
UiMR(i=0,1)
Address
When reset
03A016, 03A816
0016
Bit
symbol
Bit name
SMD0 _{Serial I/O mode}
select bits
SMD1
SMD2
Function
(During clock synchronous
serial I/O mode)
Must be fixed to 001
b2 b1 b0
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR Internal/external clock
select bit
STPS _{Stop bit length select bit}
0 : Internal clock
1 : External clock
Invalid
PRY Odd/even parity select bit Invalid
PRYE Parity enable bit
Reserved
Invalid
Must always be “0”
Function
(During UART mode)
RW
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
0 : Internal clock
1 : External clock (Note 1)
0 : One stop bit
1 : Two stop bits
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC0(i=0,1)
Address
When reset
03A416, 03AC16
0816
Bit
symbol
Bit name
CLK0 ^{BRG count source}
select bits
CLK1
Function
(During clock synchronous
serial I/O mode)
Function
(During UART mode)
b1 b0
0 0 : f1SIO or f2SIO is selected
(Note 2)
0 1 : f8SIO is selected
1 0 : f32SIO is selected
1 1 : Inhibited
b1 b0
0 0 : f1SIO or f2SIO is selected
(Note 2)
0 1 : f8SIO is selected
1 0 : f32SIO is selected
1 1 : Inhibited
RW
CRS
TXEPT
CTS/RTS function
select bit
Transmit register empty
flag
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 3)
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
completed)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 3)
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
CRD CTS/RTS disable bit
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60 and P64 function as
programmable I/O port)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60 and P64 function as
programmable I/O port)
NCH Data output select bit
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open-drain output
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open-drain output
CKPOL CLK polarity select bit
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
Must always be “0”
UFORM Transfer format select bit ^{0 : LSB first}
1 : MSB first
Must always be “0”
Note 1: Set the corresponding port direction register to “0”.
Note 2: Periperal clock select register bit PCLK1 is used to select between f1SIO and f2SIO.
Note 3: The settings of the corresponding port register and port direction register are invalid.
Figure 1.15.5. Serial I/O-related registers (2)
Renesas Technology Corp.
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